Modern digital networking devices must operate at very high speeds in order to accommodate ever increasing line speeds and large numbers of different possible output paths. Thus, it is very important to have a high-speed processor in a network device in order to be able to quickly process data packets. However, without an accompanying high-speed memory system, the high-speed network processor may not be able to temporarily store data packets at an adequate rate. Thus, a high-speed digital network device design requires both a high-speed network processor and an associated high-speed memory system.
In addition to the high-performance required, networking applications place a wide variety of memory demands on their associated memory systems. For each packet that passes through a network router that packet must be buffered such that high-speed packet-buffering services are needed. Each packet must also be routed such that very frequent routing table look-ups must be performed to determine where each packet will travel on its next network hop. Each packet will also cause a number of statistics counters to be affected such that these statistics counters must be updated. All of this packet-buffering, table look-ups, and statistics counter memory operations must be performed at very high-speeds.
To provide adequate memory services for such demanding network applications, traditional network routers generally employ multiple different types of memory technology coupled to a network processor. A high-speed network device may contain a network processor that is coupled to three or more different types of memory subsystems. For example, a first memory system may be used for packet-buffering, a second memory system may be used for storing statistics counters, and a third memory system is used for storing look-up tables. Such a memory arrangement is very complex and cumbersome. That type of memory arrangement of requires an individual connection to each different type of memory such that many input/output pins are required on the network processor and the printed circuit board layout due to the multiple memory buses. Furthermore, such a memory arrangement may use a large amount of memory such that the memory system will be expensive to implement, consume large amounts of power, and require significant amounts of printed circuit board area.
Due to the overwhelmingly complexity and high cost of conventional memory systems for high-speed network devices, it would be desirable to find an improved method of creating high-speed memory systems for network devices that require a large variety of memory services at very high speeds. Ideally, such a memory system would provide a consistent memory interface that would provide all of the different types of memory services needed by network devices.